This invention relates to a method of fabricating a dynamic random access memory (DRAM), and more particularly, to a DRAM memory cell composed of a storage capacitor and a vertical channel Insulated Gate Field Effect Transistor (IGFET) both formed in a semiconductor body, and a method of fabricating a connection (strap) between the IGFET and a plate of the capacitor.
There is a continuing trend towards increasing the capacity of DRAMS. Such an increase in capacity is best achieved by decreasing the surface area of the memory cells and increasing their packing density to increase the number of memory cells in the semiconductor body (silicon chip) that houses the DRAM. The reduction in surface area and increase in packing density can be achieved by both a decrease in the feature sizes of the elements of the DRAM, and by the use of transistors, capacitors, and interconnect structures which are three-dimensional in nature, with their active elements lying not only on the surface of the semiconductor body, but also extending down into the interior of the semiconductor body.
One technique which has been used to increase the packing density of the memory cells has been to use a vertical trench in which is formed a capacitor that serves as a storage element of the memory cell. A further technique has been to use as the access transistor a vertical channel transistor formed on the sidewall of the vertical trench in which the capacitor is formed.
FIG. 1 shows the elements of a well known prior art DRAM memory cell comprising a field effect transistor 130 and a capacitor 140. Transistor 130 has a first output 133 connected to a first plate 141 of the capacitor 140 whose second plate is connected to a common potential, typically ground potential. A connection between the output 133 and the capacitor plate 141 is made by means of an interconnection structure 150. A second output 131 of the transistor 130 is connected to a bit line 110, and a gate (control electrode) 132 of the transistor 130 is connected to a word line 120. Multiple bit lines, of which bit line 110 is one, run vertically through an array of the memory cells, and multiple word lines, of which word line 120 is one, run horizontally through the array of memory cells.
Traditionally, the transistors 130 and capacitors 140 were formed as planar devices on the surface of a semiconductor body.
FIG. 2 shows schematically the cross-section of a prior art implementation of a transistor-capacitor DRAM memory cell in which a storage capacitor 240 is formed in a lower portion of a vertical trench 260 in a semiconductor 200, and a transistor 230, which comprises a first output region 231, a second output region 233, and a gate 232, has a channel region 235 formed on a sidewall 236 in an upper portion of the vertical trench 260. In a typical embodiment semiconductor body 200 is of p-type conductivity. A relatively thick silicon dioxide insulting layer 261 is formed on a major portion 265 of a surface of the trench 260. At a bottom of the trench 260 the thick oxide layer 261 is replaced with a thinner oxide layer 243. On sidewall 236 of the surface of an upper portion of the trench 260 a thin gate oxide layer 234 is formed, and serves as the gate oxide of the transistor 230. A portion 263 of the oxide layer 261 has been removed. A lower portion of the trench 260 has been filled up to a level above the thinner oxide layer 243, and above the opening 263, with a conducting material, typically highly-doped polysilicon of n-type conductivity, which forms the first plate 241 of the capacitor 240. The second plate 242 of the capacitor 240 is formed by the semiconductor body 200. A top surface 244 of capacitor plate 241 is covered with a thick oxide layer 262. N-type dopant material diffuses from the capacitor plate 241 through the opening 263 into the semiconductor body 200 to form an n-type semiconductor region 233 which serves as the second output region 233 of the transistor 230. The portion of the trench 260 above the oxide layer 262 is filled with a conducting material, typically n-type polysilicon, to form a gate electrode 232 of the transistor 230. The first output region 231 is formed on a top surface 202 of the semiconductor body 200 and in one embodiment is of n-type conductivity. A word line 220 is formed on the surface 223 of the insulator layer 222 and contacts gate electrode 232 through an opening 221 in layer 222. A bit line 210 is formed on the surface 213 of the insulator layer 212 and contacts the second output region 231 through an opening 211 in layers 222 and 212.
The structure depicted in FIG. 2 implements the memory cell depicted in FIG. 1 in a three-dimensional structure with a conservative use of surface area of the semiconductor body 200.
FIG. 3 shows a sectional view, through the plane 3xe2x80x943 of FIG. 2, of an array of prior art memory cells. A portion of each of four trenches, 260-1, 260-2, 260-3, and 260-4 of an array of such trenches are shown. A portion of the surface of each trench is covered with the thick oxide layers 261-1, 2, 3, and 4. The trenches have been filled with conductors 241-1, 2, 3, and 4. During processing a portion of the n-type dopant of the conductors 241-1, 2, 3, and 4 diffuses through the opening 263-1, 2, 3, and 4 (not shown) and forms the output regions 233-1, 2, 3, and 4 of the transistors.
It can be seen from the drawing that output regions 233-1, 233-2, 233-3, and 233-4 extend beyond the perimeter of the trenches themselves, and, in the case of output regions 233-1 and 233-3, are considerably closer to each other than are the trenches 260-1 and 260-3 themselves. The limiting factor in determining how close to each other the trenches can be placed is a minimum allowable distance between the output regions 233-1, 2, 3, and 4, rather than the minimum feature size of the lithographic and etching technologies. The minimum allowable distance between the output regions 233-1, 2, 3, and 4 is determined by considerations of leakage and performance of the memory cells. The distance between the output regions 233-1, 2, 3, and 4 is further influenced by variations in the out-diffusion of the dopant material and the voltage of the output region with respect to the semiconductor body. If two output regions become close enough, leakage current can flow between the two output regions. This can lead to failure of the memory array.
It is desirable to have a DRAM comprising an array of memory cells each having a vertical IGFET and a capacitor formed in a trench which has greater packing density than conventional DRAMs with high yields.
The present invention is directed to a novel dynamic random access memory (DRAM) comprising an array of memory cells each comprising a vertical insulated gate field effect transistor (IGFET) having a channel region and first and second output regions, and a capacitor formed in a trench with a strap region connecting a first plate of the capacitor to the second output region, and to a method of forming same. The design and method of fabrication of the novel DRAM memory cell results in a greatly increased distance between the output regions of the transistors of adjacent memory cells. This reduces the potential for leakage between adjacent memory cells which allows adjacent cells to be placed closer to one another and thereby increases packing density.
The method of the present invention uses two masking levels to limit an opening in a thick oxide layer covering a surface of a trench to a small portion of one side of the trench. The second output region of the transistor is formed by out-diffusion of impurities from the strap region and a doped polysilicon first plate of the capacitor through this opening. One of the two masks limits the size of the opening, and the other limits the opening to one side of the trench. The first of these two masks is a mask which in a conventional process defines the location of a shallow trench isolation region (STI) which subsequently defines the lateral location of the first output region of the transistor. The second mask restrains the location of the transistor and strap region of each memory cell to a single side of the memory cell structure.
A common mask is used to define the lateral position of the first output region and the lateral positions of the channel, second output, and the strap regions. Thus the output regions, channel region, and strap region of each memory cell are laterally self-aligned with respect to each other.
From a first apparatus aspect, the present invention is directed to an array of memory cells. Each memory cell is formed in and on a semiconductor body having a top surface and comprising a vertical field effect transistor having a gate and first and second output regions separated by a channel region and a capacitor formed within a trench in the semiconductor body. A first plate of the capacitor is partially surrounded by an insulating layer and is coupled to the second output region through a strap region with the insulating layer surrounding the first plate on all sides except for a selected portion of just one side of the first plate such that the second output region, which is formed by out-diffusion of impurities from the strap region and the first plate, is limited in lateral extent so as to limit electrical leakage between second output regions of adjacent memory cells.
From a second apparatus aspect, the present invention is directed to an array of memory cells. Each memory cell is formed in and on a semiconductor body having a top surface, with the memory cell comprising a vertical field effect transistor having a gate and first and second output regions separated by a channel region and a capacitor formed within a trench in the semiconductor body. A first doped polysilicon plate of the capacitor is partially surrounded by an insulating layer and is coupled to the second output region through a doped polysilicon strap region with the insulating layer surrounding the first plate on all sides except for a selected portion of just one side of the first plate such that the second output region, which is formed by out-diffusion of impurities from the strap region and the first plate, is limited in lateral extent so as to limit electrical leakage between second output regions of adjacent memory cells and the first output region being self aligned to the channel region and to the second output region.
From a first method aspect, the present invention is directed to method of forming an array of memory cells with each memory cell fabricated in and on a semiconductor body having a top surface, each memory cell comprising a vertical field effect transistor having a gate and first and second output regions separated by a channel region and a capacitor formed within a trench in the semiconductor body with a doped polysilicon first plate of the capacitor being partially surrounded by an insulating layer and being coupled to the second output region, which is formed by out-diffusion from the strap region and the first plate, through a doped polysilicon strap region with the insulating layer surrounding the first plate on all sides except for a selected portion of just one side of the first plate such that the second output region is limited in lateral extent to limit electrical leakage between second output regions of adjacent memory cells and the first output region being self aligned to the channel region and the second output region, the second output region being formed by out-diffusion of impurities from the strap and first plate regions, starting at a point in which separated trenches have been formed in the semiconductor body and a relatively thin oxide layer has been formed at a bottom surface of each of the trenches and along lower portions of the sidewalls of the trenches which intersect the bottom surface of the trenches and a relatively thick layer of oxide has been formed on the remaining portions of the sidewalls, and the trenches are filled with a first doped polysilicon. The method comprises the step of using shallow trench isolation regions to define the lateral extent of each of the first output regions, and the lateral extent of each of the second output regions, the channel regions and the strap regions.
From a first method aspect, the present invention is directed to a method of forming an array of memory cells with each memory cell fabricated in and on a semiconductor body having a top surface. Each memory cell comprises a vertical field effect transistor having a gate and first and second output regions separated by a channel region and a capacitor formed within a trench in the semiconductor body with a doped polysilicon first plate of the capacitor being partially surrounded by an insulating layer and being coupled to the second output region, which is formed by out-diffusion from the strap region and the first plate, through a doped polysilicon strap region with the insulating layer surrounding the first plate on all sides except for a selected portion of just one side of the first plate such that the second output region is limited in lateral extent to limit electrical leakage between second output regions of adjacent memory cells and the first output region being self aligned to the channel region and the second output region, the second output region being formed by out-diffusion of impurities from the strap and first plate regions, starting at a point in which separated trenches have been formed in the semiconductor body and a relatively thin oxide layer has been formed at a bottom surface of each of the trenches and along lower portions of the sidewalls of the trenches which intersect the bottom surface of the trenches and a relatively thick layer of oxide has been formed on the remaining portions of the sidewalls, and the trenches are filled with a first doped polysilicon. The method comprising the steps of: etching the first doped polysilicon from an upper portion of each trench down to a level above the thin oxide covering the bottom portions of the sidewalls of the trenches; forming a layer of silicon nitride over the exposed portions of the relatively thick oxide layer and a top surface of the remaining portion of the doped polysilicon; filling portions of the trenches lined with the layer of silicon nitride with a second doped polysilicon; forming shallow trench isolation regions extending from a top surface of the semiconductor body into the semiconductor body to partially define locations therein in which the first output region and the channel region of the transistor and the strap region are to be formed; removing portions of the second doped polysilicon not covered by the shallow trench isolation regions down to the silicon nitride layer formed on the top surface of the previously remaining portion of the first doped polysilicon which forms the first plate of the capacitor to define two sides of the trench, one of which is to contain the strap region and the channel region and a portion of one side of the second output region; forming a mask to define which of the two sides of the trench previously defined will contain the strap region; removing portions of the silicon nitride layer not covered by the mask or by the remaining second doped polysilicon; removing an exposed portion of the relatively thick oxide layer which is on the sidewalls of the trenches down to and below a top surface of the remaining portion of the first doped polysilicon which forms the first plate of each of the capacitors; removing the mask; removing the silicon nitride layer from a sidewall of the trench and a top portion over the remaining portion of the first doped polysilicon which is to become the first capacitor plate so as to expose the thick oxide layer on a sidewall of the trench; and filling the region of the trench in which the strap region is to be formed with a third doped polysilicon to from the strap region.
The invention will be better understood from the following more detailed description in conjunction with the accompanying drawing and claims.